Tuesday Opening Ceremony & Keynote Presentations
Heterogeneous Integration: Developing a New Generation of 3D Chiplet Packaging Technology for Next Generation Devices & Emerging Opportunities in Heterogeneous design of XPU
ntegration: Developing a New Generation of 3D Chiplet Packaging Technology for Next Generation Devices
Currently, the best solution for optimizing silicon systems for any given new workload is to create a system on chip (SoC), monolithic chip. But this gets more expensive with demand for high-performance AI, HPC applications and advanced Si node technology. One way of reducing the cost of Silicon systems for emerging workloads would be to use chiplet technology. From a commercial standpoint, this approach makes a lot of sense. The cost of a highly integrated SoC can be very high- so high it’s prohibitive for many. Furthermore, the complexity of such highly integrated semiconductor systems makes manufacturing more challenging: there is a direct correlation between higher complexity and yield loss. The package technology now sits in the center of the universe for the next generation of devices.
In this presentation, various chiplet packaging technologies including MCM, SiP, integrated wafer level packaging solutions such as 2.5D, 3D and FOWLP will be introduced. These solutions have demonstrated their unique advantages in many applications that require high-end chips (such as CPU, GPU, AI, FPGA, network) or low-end chips (for IoT and wearable devices) in combination with high bandwidth SRAM/DRAM memory.
Additionally, the challenges and opportunities of a new generation of chiplet packaging and decoupling capacitor solutions will be discussed from a system/package co-design, performance and supply chain point of view.
Emerging Opportunities in Heterogeneous design of XPU
We are entering an era of designing products based on heterogeneous integration on the package, where disaggregated chiplets are stitched together seamlessly through packaging to derive a quasi-monolithic operation. The talk will focus on product drivers and architectural complexity and the need for execution focus on product cost and TTM. The need for a disciplined approach to efficiently develop “validated IP” at the die-package interfaces will be highlighted. This calls for tight collaboration between physical design, electrical modelling, tools and flows in the design cycle.